Develop advanced UVM-based testbenches and achieve functional coverage closure for SoC, IP, ASIC, FPGA, and NoC projects. Ensure first-pass silicon success through rigorous verification strategies.

Key Skills: SystemVerilog UVM, functional coverage, assertions, random stimulus generation, debug.

📍 Location:

• Singapore
• India (Bengaluru/Hyderabad/Noida)
• Malaysia
• Vietnam